RES — Reset

---

Description

RES (Reset) clears the accumulator and status bits of the timer, counter or control structure named on it, every scan its rung is true. It is drawn as a coil, because that is what it is: an output that acts on its rung. RES is the only way to clear an RTO, the only way to bring a counter back to zero, and the only way to restart a sequencer or bit shift whose position has reached the end. Use it wherever a total, a count or a position must start over on command. Do not use RES on a TOF; see Notes.

---

Operands

Operand	Type	Format	Valid Range	Required	Description
Tag	TIMER, COUNTER or CONTROL	Tag name or Array[n]	Any tag of those three types, including an array element such as TMR[0]	Yes	The structure to reset. Name the base tag, never a member: Batch, not Batch.ACC.

What is cleared depends on the type:

Tag type	Set to zero	Cleared	Left alone
TIMER	.ACC	.EN, .TT, .DN	.PRE
COUNTER	.ACC	.DN, .OV, .UN	.PRE, .CU and .CD (the rung-edge memory)
CONTROL	.POS	.EN, .EU, .DN, .EM, .ER, .UL, .IN, .FD	.LEN, the rung-edge memory

---

Scan Behavior

Prescan

Nothing.

Rung-condition-in is false

Nothing. The target keeps its values.

Rung-condition-in is true

The target is reset as in the table above, on this scan and every scan the rung stays true. A timer whose own rung is true starts timing again from zero on the next scan. A counter or control structure whose own rung is still held true does not count or shift again until that rung has gone false and true once more.

Postscan

Nothing.

---

Example

Scenario: The batch counter from the CTU page counts completed cycles toward a batch of five. When the batch is done a latch bit is set (elsewhere, OTL CtnDn_Latch from Counter.DN) and the operator clears it after unloading. While that latch is held, a RES holds the counter at zero so the next batch starts clean.

Tags:

• Cycle_Complete — Cycle complete, BOOL
• Counter — COUNTER, Preset 5
• CtnDn_Latch — Count-done latch, BOOL

Rung 1 (count, with the reset on an output branch):

—|XIC Cycle_Complete|——┬——[CTU Counter  Preset 5]——————┬——
                       └——|XIC CtnDn_Latch|——(RES Counter)——┘

The RES is on an output branch below the CTU, so it is gated by the rung’s own condition as well as its leg’s: it resets only while Cycle_Complete and CtnDn_Latch are both true. Put it on its own rung with only XIC CtnDn_Latch in front if it should reset regardless of the cycle signal.

In the screenshot both are true. The CTU’s rung is true and CU is lit, but the RES on the branch below is resetting the counter every scan, so the Accum sits at 0 and DN stays dark. The ring is lit because its rung is true.

Clear CtnDn_Latch: the RES releases. The CTU does not count on that scan even though its rung is still true, because RES keeps the rung-edge memory; the Accum goes to 1 on the next false-to-true transition of Cycle_Complete.

---

See Also

• RTO — Retentive Timer On (clears only by RES)
• CTU — Count Up (the self-resetting batch counter idiom)
• TOF — Timer Off Delay (never reset it with RES)
• BSL — Bit Shift Left (restart a filled shift with RES on its CONTROL)
• SQO — Sequencer Output (return to step 0 with RES)
• Timer and Counter Instructions — Category index

---

Notes

One tag per RES. A RES resets exactly one structure. Two structures need two RES instructions; they can share a rung through an output branch.

Do not use RES on a TOF. RES clears DN and ACC at once, which ends the off delay immediately and turns the output off with no delay at all. The SLC 500 manual carries the same warning. Cancel a TOF by making its rung true.

Self-resetting idioms. XIC Batch.DN → RES Batch on its own rung gives a counter that counts to the preset, fires DN for one scan, and starts over. XIC Cycle.DN → RES Cycle does the same for an RTO. Place the reset rung after the rung that uses DN, so the DN scan is seen before it is cleared.

A CONTROL’s length is kept. RES on a sequencer, bit shift, FIFO or LIFO control returns .POS to 0 and clears the status bits but leaves .LEN, which is that structure’s preset.

Edge memory is kept. Counters and control structures act on their rung’s rising edge. RES does not forget that the rung was true, so a rung held through the reset cannot count or shift again on the very next scan. Timers have no edge memory and restart.

A RES needs no one-shot. Resetting an already-cleared structure changes nothing, so a RES rung held true for many scans is harmless.