BSR — Bit Shift Right

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Description

BSR (Bit Shift Right) shifts every bit of a register one place toward bit 0 each time its rung goes from false to true. The Bit Address enters at the top, position Length − 1, and bit 0 falls out into the control tag’s UL member. It is BSL run the other way, for a line whose stations are numbered from the far end, or a register that must be read from bit 0 as the “oldest” position. Do not put an ONS ahead of it; the instruction detects its own rising edge.

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Operands

Operand	Type	Format	Valid Range	Required	Description
Control	CONTROL tag	Tag or Tag[n]	One BSR per control tag	Yes	Holds LEN, POS and the status bits.
File	INT or DINT tag, scalar or array	Tag (never an element)	Any	Yes	The shift register; capacity 16 bits per INT, 32 per DINT, times the array size.
Bit	BOOL tag, INT/DINT bit or literal	Tag, Word.n, 0, 1	Any resolvable bit	Yes	The value shifted in at bit Length − 1.
Length	Whole number	8, 16, 84	1 to the register’s capacity in bits	Yes	How many bits take part. Bits above Length are cleared on every shift.

Everything said about capacity and addressing on the BSL page applies here.

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Scan Behavior

Prescan

LEN is loaded from the instruction’s Length and POS starts at 0. The status bits and UL are clear.

Rung-condition-in is false

EN is cleared. Nothing shifts; the register and every status bit hold.

Rung-condition-in is true

On the scan the rung turns true, one shift happens: UL takes bit 0, every bit moves down one place, and the Bit operand enters at position Length − 1. POS counts the shift up to Length; DN sets once POS reaches Length. No further shift happens until the rung has been false again.

Postscan

Nothing.

Condition	EN	DN	UL	POS	Register
Power-up	0	0	0	0	as loaded
Rung false	0	holds	holds	holds	holds
False → true	1	POS ≥ LEN	bit 0 before the shift	+1, to LEN	shifted
Held true	1	holds	holds	holds	holds
RES on the control	0	0	0	0	holds

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Member Bits

Bit	Mnemonic	Data type	Set by	Cleared by	Operation description
Enable	.EN	BOOL	The rung being true	The rung being false, or RES	Mirrors the rung condition.
Enable unload	.EU	BOOL	Never	RES	Reserved; BSR does not use it.
Done	.DN	BOOL	POS reaching LEN	RES	The register has been shifted LEN times since the last reset.
Empty	.EM	BOOL	Never	RES	Not used by BSR.
Error	.ER	BOOL	Never	RES	Reserved. Bad operands are refused at validation.
Unload	.UL	BOOL	The bit that left bit 0 on the last shift	The next shift, or RES	Holds the bit that fell out of the bottom of the register.
Inhibit	.IN	BOOL	Never	RES	Reserved.
Found	.FD	BOOL	Never	RES	Not used by BSR.
Length	.LEN	INT	The instruction’s Length at power-up	Never (RES preserves it)	Bits in the register; clamped to the file’s capacity at runtime.
Position	.POS	INT	Each shift, up to LEN	RES	Counts shifts since the last reset.

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Example

Scenario: The same reject-tracking register as the BSL example, on a line that indexes the other way. The reject flag enters at position 7 and rides down to bit 0, where the blow-off reads UL.

Tags:

• Index_R — Conveyor index pulse, BOOL
• Reject — Infeed reject flag, BOOL
• Track_R — Reject register, INT
• BSR_Ctl — Control, CONTROL, Length 8

Rung 1:

—] [Index_R———[BSR BSR_Ctl  Track_R  Reject  8]———

Scan 1 — Index_R = 0. Track_R reads 133 (bits 7, 2 and 0 set) and Reject reads 1. The rung is false: Position 0, DN and UL dark. The BSL rung above it is the BSL page’s example, parked at the same values.

Scan 2 — Index_R = 1. One shift: bit 0 leaves into UL, everything moves down, the reject flag enters at bit 7. Track_R reads 194, UL is lit, Position 1. The BSL rung above has already taken its own shift and shows 11.

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Binary Result

BSR — File Track_R (INT), Length 8, Bit = 1

            15 14 13 12  11 10  9  8   7  6  5  4   3  2  1  0
Before       0  0  0  0   0  0  0  0   1  0  0  0   0  1  0  1   = 133
After        0  0  0  0   0  0  0  0   1  1  0  0   0  0  1  0   = 194
                                       ^                      ^
                          Bit operand shifted in       bit 0 shifted out
UL (bit 0 shifted out) = 1
Bits 8..15 are outside Length and are cleared.

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Control Tag Errors and Troubleshooting

Error definitions

.ER cause	Condition that sets it	.POS / status value	Meaning
None	.ER is never set by LadderIDE	—	A File that is not an INT/DINT tag, an element reference, or a Length outside 1..capacity is refused when the project is validated.

Troubleshooting hints

Symptom: The register shifts the wrong way. Likely cause: BSL and BSR look alike on the rung. Fix: Read the block title; the Bit operand enters at bit 0 for BSL and at bit Length − 1 for BSR.

Symptom: .UL is never set although bits reach the bottom. Likely cause: UL holds the bit that leaves on the most recent shift only; it is overwritten by the next shift. Fix: Read .UL on the scan after the shift, or latch it with OTL.

Symptom: .DN is set and stays set. Likely cause: .POS has reached .LEN. Fix: RES the control tag at the start of a batch.

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See Also

• BSL — Bit Shift Left (capacity, addressing and the long-register notes)
• RES — Reset
• Shift/Sequencer Instructions — Category index

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Notes

Which end is “in”. BSL fills from bit 0 upward, BSR from the top downward. Pick the one whose bit numbering matches the station numbering on the machine so Track.n reads as station n.

The block colours neutral. Watch the rung wire, the Position row and the DN/UL indicators.