BSL — Bit Shift Left

---

Description

BSL (Bit Shift Left) shifts every bit of a register one place toward the high end each time its rung goes from false to true. The Bit Address enters at bit 0 and the bit that falls off the top lands in the control tag’s UL member. Use BSL to track parts along a conveyor: each index pulse shifts the register, a sensor at the infeed sets the bit that enters, and a station downstream reads the bit that has travelled to its position. Do not put an ONS ahead of a BSL; the instruction detects its own rising edge, and a series ONS only adds a scan of confusion. A rung held true shifts exactly once.

---

Operands

Operand	Type	Format	Valid Range	Required	Description
Control	CONTROL tag	Tag or Tag[n]	One BSL per control tag	Yes	Holds LEN, POS and the status bits.
File	INT or DINT tag, scalar or array	Tag (never an element)	Any	Yes	The shift register. An INT holds 16 bits, a DINT 32, an array dims times that; the elements chain into one register.
Bit	BOOL tag, INT/DINT bit or literal	Tag, Word.n, 0, 1	Any resolvable bit	Yes	The value shifted in at bit 0.
Length	Whole number	8, 16, 84	1 to the register’s capacity in bits	Yes	How many bits take part. Bits above Length are cleared on every shift.

Capacity. Length counts bits, not elements: an INT file may use 1 to 16, a DINT 1 to 32, a DINT[3] up to 96. Name the array, not an element; the register spans the whole file, bit n living at element n / width, bit n % width. A Length past the capacity is a validation error.

Reading a position. Bit 5 of an INT file Track is Track.5; bit 40 of a DINT[3] file Pockets is Pockets[1].8.

---

Scan Behavior

Prescan

LEN is loaded from the instruction’s Length and POS starts at 0. The status bits and UL are clear. The File keeps whatever the tags were loaded with.

Rung-condition-in is false

EN is cleared. Nothing shifts; the register and every status bit hold. The false state arms the next edge.

Rung-condition-in is true

On the scan the rung turns true, one shift happens: UL takes the bit at position Length − 1, every bit moves up one place, the Bit operand enters at bit 0, and bits above Length are cleared. POS counts the shift, up to Length, and DN sets once POS reaches Length. EN is set while the rung stays true, and no further shift happens until the rung has been false again.

Postscan

Nothing.

Condition	EN	DN	UL	POS	Register
Power-up	0	0	0	0	as loaded
Rung false	0	holds	holds	holds	holds
False → true	1	POS ≥ LEN	bit LEN − 1 before the shift	+1, to LEN	shifted
Held true	1	holds	holds	holds	holds
RES on the control	0	0	0	0	holds

---

Member Bits

Bit	Mnemonic	Data type	Set by	Cleared by	Operation description
Enable	.EN	BOOL	The rung being true	The rung being false, or RES	Mirrors the rung condition so other logic can see the instruction is being driven.
Enable unload	.EU	BOOL	Never	RES	Reserved for FIFO/LIFO compatibility; BSL does not use it.
Done	.DN	BOOL	POS reaching LEN	RES	The register has been shifted LEN times since the last reset, so every position has been refilled.
Empty	.EM	BOOL	Never	RES	Not used by BSL.
Error	.ER	BOOL	Never	RES	Reserved. LadderIDE reports a bad File or Length at validation time instead.
Unload	.UL	BOOL	The bit that left the top of the register on the last shift	The next shift, or RES	Holds the bit that fell off bit LEN − 1, so a station past the end of the register can act on it.
Inhibit	.IN	BOOL	Never	RES	Reserved.
Found	.FD	BOOL	Never	RES	Not used by BSL.
Length	.LEN	INT	The instruction’s Length at power-up	Never (RES preserves it)	Bits in the register. May be written from the Tag Browser online; the firmware clamps it to the file’s capacity.
Position	.POS	INT	Each shift, up to LEN	RES	Counts shifts since the last reset.

---

Example

Scenario: A conveyor carries parts through eight stations. A vision check at the infeed flags a reject; the flag rides along the register with the part and a blow-off at station 8 acts on the bit that leaves the register.

Tags:

• Index_L — Conveyor index pulse, BOOL
• Reject — Infeed reject flag, BOOL
• Track_L — Reject register, INT
• BSL_Ctl — Control, CONTROL, Length 8

Rung 1:

—] [Index_L———[BSL BSL_Ctl  Track_L  Reject  8]———

Scan 1 — Index_L = 0. Track_L reads 133 (bits 7, 2 and 0 set) and Reject reads 1. The rung is false: Position 0, DN and UL dark. The BSR rung below it is the mirror example from the BSR page, parked at the same values.

Scan 2 — Index_L = 1. One shift: bit 7 leaves into UL, everything moves up, the reject flag enters at bit 0. Track_L reads 11, UL is lit, Position 1.

Seven more index pulses bring Position to 8 and set DN. The register keeps shifting after that; DN only says every position has been refilled since the last RES.

---

Binary Result

BSL — File Track_L (INT), Length 8, Bit = 1

            15 14 13 12  11 10  9  8   7  6  5  4   3  2  1  0
Before       0  0  0  0   0  0  0  0   1  0  0  0   0  1  0  1   = 133
After        0  0  0  0   0  0  0  0   0  0  0  0   1  0  1  1   = 11
                                       ^                      ^
                              bit 7 shifted out       Bit operand shifted in
UL (bit 7 shifted out) = 1
Bits 8..15 are outside Length and are cleared.

---

Control Tag Errors and Troubleshooting

Error definitions

.ER cause	Condition that sets it	.POS / status value	Meaning
None	.ER is never set by LadderIDE	—	A File that is not an INT/DINT tag, an element reference, or a Length outside 1..capacity is refused when the project is validated, before download.

Troubleshooting hints

Symptom: Nothing shifts although the rung goes true. Likely cause: The rung never returns to false between events, so there is no rising edge; or an ONS ahead of the BSL pulses for one scan while the rung is evaluated on the next. Fix: Drive the rung from the index sensor directly and remove any series one-shot. Watch .EN follow the rung.

Symptom: .DN is set and stays set. Likely cause: .POS has reached .LEN; DN is latched until reset. Fix: Use RES on the control tag at the start of a batch, or ignore DN if you only need the register contents.

Symptom: Bits appear at the top of the word that were never shifted in. Likely cause: Something else writes the File tag, or Length is smaller than the bits you are reading. Bits above Length are cleared on each shift, so a stray bit there was written between shifts. Fix: Cross-reference the File tag; make Length cover every position you read.

---

See Also

• BSR — Bit Shift Right
• RES — Reset (clears POS and the status bits, keeps LEN)
• XIC — Examine If Closed (read a position with Track.n)
• Shift/Sequencer Instructions — Category index

---

Notes

Long registers. DINT[3] with Length 84 tracks 84 pockets in one instruction. The words chain, so a bit moving from element 0 bit 31 lands in element 1 bit 0.

Reading bits online. The monitor broadcasts every element of a shift file, so the register is visible in the Tag Browser while online.

The block colours neutral. Watch the rung wire, the Position row and the DN/UL indicators.